When a signal is transmitted long distance through copper traces or transmission line, noise is introduced in the signal. The receiver at the receiving end does not see a perfect square wave. The signal gets worst when ground bounce and supply bounce (because of pin package inductance) make logic high and low level a damped sinusoidal. In such cases, a Schmitt trigger circuit is frequently used at the receiver end to filter the noise.
A Schmitt trigger is an electronic circuit used to turn a signal having slow or asymmetrical transition into a signal with a sharp transition region. Schmitt trigger circuit cleans up the input signal from noise and provides very sharp transition. However, Schmitt trigger circuits are slower and consume more power compared to similar non-Schmitt circuit. Moreover, Schmitt circuit characteristic is very much dependent on process and temperature variations because process and temp directly affects the threshold voltages, which is not under control. Once chip is fabricated, process is fixed but operating temp and voltage change the low and high level transition point and hence the hysteresis. For very slow transition and long distance transmission, a Schmitt trigger circuit with large value of hysteresis is required.
FIG. 1 shows the diagram referred to in the U.S. Pat. No. 5,461,338. Bias potential generation circuits 5 and 6 generate bias voltage only if the circuit is in normal mode (not in standby mode). This bias generation circuits 5 and 6 generate two separate signals for the well of PMOS and substrate of NMOS which forward biases the body-source of the CMOS transistors. It helps in reduction of the threshold voltages of the CMOS devices and hence better speed is achieved. According to the claim of this circuit, bias potential must be smaller than the flat band voltage between semiconductor substrate and source junction of the devices. This bias potential is not generated in standby mode to reduce power. A switching circuit has been introduced between the body of the devices and the source junction to take care of the standby signal. A separate circuit generates the said standby signal 4.
This concept saves power in standby mode and achieves significant improvement in the speed especially when a high voltage device is operated at low voltages. But this circuit does not take care of the process, temperature or supply voltage variations. So it is very sensitive to the process and environmental conditions. It may lead to more power consumption if bias voltage becomes greater than the flat-band voltage.
FIG. 2 is another prior art U.S. Pat. No. 6,515,534 on the device control to make speed better even at very low supply voltages. Diodes D1 and D2 are the parasitic diodes formed between body and source/drain junction of the PMOS transistor 21. INV3 and INV4 are the two CMOS inverters, which detect the gate signal of the PMOS transistor 21 and generate the bias signal for the body of the PMOS transistor 21. Whenever gate signal goes low to turn PMOS transistor 21 ON, the body (well) of the PMOS transistor 21 also goes low and diodes D1 and D2 are forward biased. This reduces the threshold voltage of the PMOS transistor 21 and provides more drain current through diodes D1 and D2, which increase the speed of the PMOS transistor 21.
This circuit detects the signal from the gate of the device and biases the body accordingly so that device is faster. Since large amount of current flows through the diodes, if MOS size is large (as in case of IOs), latchup can be a problem. This circuit also does not take care of the changes in process and environmental conditions.
Since Schmitt trigger circuit has been taken an example for the one embodiment of the new concept, few prior art on Schmitt trigger circuits have been discussed.
FIG. 3 is a schematic of a widely used conventional Schmitt trigger circuit. Four stacked parallel input MOSFETS P1, P2, N1 and N2 are coupled by their respective gate electrodes to the trigger input IN. Depending on the transition of IN, VP or VN signals are generated which are controlled by the transistor size ratio P3/P1 and N3/N1. M1 and M2 make an inverter to provide a sharp transition at OUT. P3 and N3 form a feedback structure to control PMOS and NMOS. If IN is low then P3 is OFF and N3 is ON, OUT is low. As IN increases, NMOS N1 begins to turn ON and VN starts to fall down. The trip point is defined when IN=Vtn2+VN that is when NMOS N2 turns ON. When N2 turns ON, drain of N2 starts falling down and turns NMOS N3 OFF. Once N2 is ON, transition is very fast. If transistor size of N2 is large compared to N1 and N3 then trip point (Vih) is accurately decided by the ratio of N3/N1. Similarly Vil is decided by the ratio of P3/P1. This circuit is sensitive to the VDDS (positive supply voltage) and process because Vth of P3 and N3 keeps on changing as node VP or VN goes up or comes down respectively with IN. At low supply voltage this circuit does not work properly.
All the above circuits including Schmitt trigger as discussed above are sensitive or more sensitive to process, temperature and voltage variations. In a noisy environment, a very stable circuit is required which should be independent of process and environmental conditions for optimum performance. In such a case a process and environmental adaptive circuit is required which will stabilize the output.
Also most of the prior arts provide large values of hysteresis at high voltage of operation, but are not efficient at low voltage (1.8V or 2.5V) because of threshold variation.